Program status word

The program status word^{[lower-alpha 1]} (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/360^[1] and its successors,^[2]^[3]^[4]^[5]^[6] and follows the IBM convention of numbering bits starting with 0 as the leftmost (most significant) bit.

Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.

Contained within the PSW are the two bit condition code, representing zero, positive, negative, overflow, and similar flags of other architectures' status registers. Conditional branch instructions test this encoded as a four bit value, with each bit representing a test of one of the four condition code values, 2³ + 2² + 2¹ + 2⁰. (Since IBM uses big-endian bit numbering, mask value 8 selects code 0, mask value 4 selects code 1, mask value 2 selects code 2, and mask value 1 selects code 3.)

The 64-bit PSW describes (among other things)

Interrupt masks
Privilege states
Condition code
Instruction address

In the early instances of the architecture (System/360 and early System/370), the instruction address was 24^{[lower-alpha 2]} bits; in later instances (XA/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits.

In the present instances of the architecture (z/Architecture), the instruction address is 64 bits and the PSW itself is 128 bits.

The PSW may be loaded by the LOAD PSW instruction (LPSW or LPSWE). Its contents may be examined with the Extract PSW instruction (EPSW).

Format

S/360

On all but 360/20,^{[lower-alpha 3]} the PSW has the following formats. S/360 Extended PSW format only applies to the 360/67 with bit 8 of control register 6 set.

IBM S/360 PSW formats

S/360 Standard PSW^[11]

System Mask

Key

A

M

W

P

Interruption Code^[12]

0

7

8

11

12

13

14

15

16

31

ILC

CC

Program
Mask

Instruction Address

32

33

34

35

36

39

40

63

S/360 Standard PSW abbreviations

Bits

Field

Meaning

0-7

SM

System Mask
Bit	Meaning
0	Channel 0 mask
1	Channel 1 mask
2	Channel 2 mask
3	Channel 3 mask
4	Channel 4 mask
5	Channel 5 mask
6	Channel 6 mask
7	External Mask

8-11

Key

PSW key

12

A

ASCII

13

M

Machine-check mask

14

W

Wait state

15

P

Problem state

16-31

IC

Interruption Code^[13]

32-33

ILC

Instruction-Length Code^[14]

34-35

CC

Condition Code

36-39

PM

Program Mask
Bit	Meaning
36	Fixed-point overflow
37	Decimal overflow
38	Exponent underflow
39	Significance

40-63

IA

Instruction Address

S/360 Extended PSW^[15]

spare

24/32
Bit
Mode

Tran
Ctrl

I/O
Mask

Ext.
Mask

Key

A

M

W

P

ILC

CC

Program
Mask

spare

0

3

4

5

6

7

8

11

12

13

14

15

16

17

18

19

20

23

24

31

Instruction Address

32

63

S/360 Extended PSW abbreviations

Bits

Field

Meaning

0-3

Spare (must be 0)

4

24/32-bit Address mode

5

Translation Control

6

IO

I/O Mask (Summary)

7

EX

External Mask (Summary)

8-11

Key

Protection Key

12

A

ASCII

13

M

Machine-check mask

14

W

Wait state

15

P

Problem state

16-17

ILC

Instruction-Length Code^[16]

18-19

CC

Condition Code

20-23

PM

Program Mask
Bit	Meaning
20	Fixed-point overflow
21	Decimal overflow
22	Exponent underflow
23	Significance

24-31

Spare

32-63

IA

Instruction Address

S/370

IBM S/370 PSW formats

S/370 Basic Control mode PSW^[17]

Chan.
Mask

I
O

E
X

Key

0

M

W

P

Interruption Code

0

1

2

4

5

6

7

8

11

12

13

14

15

16

31

ILC

CC

Program
Mask

Instruction Address

32

33

34

35

36

39

40

63

S/370 BC mode PSW abbreviations

Bits

Field

Meaning

0-5

Channel Masks for channels 0-5

6

IO

I/O Mask for channels > 5

7

EX

External Mask

8-11

Key

PSW key

12

E=0

Basic Control mode

13

M

Machine-check mask

14

W

Wait state

15

P

Problem state

16-31

IC

Interruption Code^[18]

32-33

ILC

Instruction-Length Code^[19]

34-35

CC

Condition Code

36-39

PM

Program Mask
Bit	Meaning
36	Fixed-point overflow
37	Decimal overflow
38	Exponent underflow
39	Significance

40-63

IA

Instruction Address

S/370 Extended Control mode PSW^[20]

0

R

0

T

I
O

E
X

Key

1

M

W

P

S

0

CC

Program
Mask

0

1

2

4

5

6

7

8

11

12

13

14

15

16

17

18

19

20

23

24

31

0

Instruction Address

32

39

40

63

S/370 EC mode PSW abbreviations

Bits

Field

Meaning

1

R

PER Mask

5

T

DAT mode

6

IO

I/O Mask; subject to channel mask in CR2

7

EX

External Mask; subject to external subclass mask in CR0

8-11

Key

PSW key

12

E=1

Extended Control mode

13

M

Machine-check mask

14

W

Wait state

15

P

Problem state

16

S

Address-Space Control
0=primary-space mode
1=Secondary-space mode

18-19

CC

Condition Code

20-23

PM

Program Mask
Bit	Meaning
20	Fixed-point overflow
21	Decimal overflow
22	Exponent underflow
23	Significance

40-63

IA

Instruction Address

S/370 Extended Architecture (S/370-XA)

IBM Extended Architecture (XA) PSW format

Extended Architecture Extended Control mode PSW^[21]

0

R

0

T

I
O

E
X

Key

1

M

W

P

S

0

CC

Program
Mask

0

1

2

4

5

6

7

8

11

12

13

14

15

16

17

18

19

20

23

24

31

A

Instruction Address

32

33

63

S/370-XA EC mode PSW abbreviations

Bits

Field

Meaning

1

R

PER Mask

5

T

DAT mode

6

IO

I/O Mask; subject to channel mask in CR2

7

EX

External Mask; subject to external subclass mask in CR0

8-11

Key

PSW key

12

E=1

Extended Control mode

13

M

Machine-check mask

14

W

Wait state

15

P

Problem state

16

S

Address-Space Control
0=primary-space mode
1=Secondary-space mode

18-19

CC

Condition Code

20-23

PM

Program Mask
Bit	Meaning
20	Fixed-point overflow
21	Decimal overflow
22	Exponent underflow
23	Significance

32

A

Addressing mode
0=24 bit; 1=31 bit

33-63

IA

Instruction Address

Enterprise Systems Architecture (ESA)

IBM Enterprise Systems Architecture (ESA) PSW format

Enterprise Systems Architecture Extended Control mode PSW^[22]^[23]

0

R

0

T

I
O

E
X

Key

1

M

W

P

AS

CC

Program
Mask

0

1

2

4

5

6

7

8

11

12

13

14

15

16

17

18

19

20

23

24

31

A

Instruction Address

32

33

63

ESA EC mode PSW abbreviations

Bits

Field

Meaning

1

R

PER Mask

5

T

DAT mode

6

IO

I/O Mask; subject to channel mask in CR2

7

EX

External Mask; subject to external subclass mask in CR0

8-11

Key

PSW key

12

E=1

Extended Control mode

13

M

Machine-check mask

14

W

Wait state

15

P

Problem state

16-17

AS

Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode

18-19

CC

Condition Code

20-23

PM

Program Mask
Bit	Meaning
20	Fixed-point overflow
21	Decimal overflow
22	Exponent underflow^{[lower-alpha 4]}
23	Significance^{[lower-alpha 5]}

32

A

Addressing mode
0=24 bit; 1=31 bit

33-63

IA

Instruction Address

z/Architecture

IBM z/Architecture PSW formats

z/Architecture long PSW^[24]

0

R

0

T

I
O

E
X

Key

0

M

W

P

AS

CC

Program
Mask

R
I

0

E
A

0

1

2

4

5

6

7

8

11

12

13

14

15

16

17

18

19

20

23

24

30

31

B
A

0

32

33

63

Instruction Address

64

95

Instruction Address (Continued)

96

127

Long PSW abbreviations

Bits

Field

Meaning

1

R

PER Mask

5

T

DAT mode

6

IO

I/O mask

7

EX

External Mask

8-11

Key

PSW key

12

E=0

Must be zero for LPSWE

13

M

Machine-check mask

14

W

Wait state

15

P

Problem state

16-17

AS

Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode

18-19

CC

Condition Code

20-23

PM

Program Mask
Bit	Meaning
20	Fixed-point overflow
21	Decimal overflow
22	HFP Exponent underflow
23	HFP Significance

24

RI

Reserved for IBM

31

EA

Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero

32

BA

Basic Addressing mode
0=24 or 64; 1=31

64-127

IA

Instruction Address

z/Architecture short PSW^[25]

0

R

0

T

I
O

E
X

Key

1

M

W

P

AS

CC

Program
Mask

R
I

0

E
A

0

1

2

4

5

6

7

8

11

12

13

14

15

16

17

18

19

20

23

24

25

30

31

B
A

Instruction Address

32

33

63

Short PSW abbreviations

Bits

Field

Meaning

1

R

PER Mask

5

T

DAT mode

6

IO

I/O mask

7

EX

External Mask

8-11

Key

PSW key

12

E=1

Must be one for LPSW

13

M

Machine-check mask

14

W

Wait state

15

P

Problem state

16-17

AS

Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode

18-19

CC

Condition Code

20-23

PM

Program Mask
Bit	Meaning
20	Fixed-point overflow
21	Decimal overflow
22	HFP Exponent underflow
23	HFP Significance

24

RI

Reserved for IBM

31

EA

Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero

32

BA

Basic Addressing mode
0=24 or 64; 1=31

33-63

IA

Instruction Address

Notes

↑ The nomenclature varies among architectures.
↑ However, a 360/67^[7] equipped with the Extended Dynamic Address Translation^[8] feature has a 32-bit mode selected by bit 4 of the PSW^[9] in Extended PSW mode^[8] (Control Register 6, bit 8^[10]).
↑ Despite the name, the 350/20 does not adhere to the S/360 architecture.
↑ Bit 22 is renamed as HFP exponent underflow in ESA/390
↑ Bit 23 is renamed as HFP significance in ESA/390

References

↑ S360.
↑ S370.
↑ S370-XA.
↑ S370-ESA.
↑ S390-ESA.
↑ z.
↑ func67.
1 2 func67, p. 57, Glossary.
↑ func67, p. 15, Instruction Fetching and Execution.
↑ func67, p. 16, Table 4. Control Registers.
↑ S360, p. 15, Program Status Word.
↑ S360, pp. 15–16, Interruption.
↑ S370, pp. 15–16, Interruption.
↑ S370, p. 156, Instruction-Length Code.
↑ func67, pp. 15–16, Instruction Fetching and Execution.
↑ S360, p. 156, Instruction-Length Code.
↑ S370, pp. 4-8 –&#32, 4–9, Program-Status Word Format in BC Mode.
↑ S370, pp. 6-3 –&#32, 6–5, Interruption Action.
↑ S370, pp. 6-7 –&#32, 6–9, Instruction-Length Code.
↑ S370, pp. 4-6 –&#32, 4–7, Program-Status Word Format in EC Mode.
↑ S370-XA, p. 4-5, Program-Status-Word Format.
↑ S370-ESA, p. 4-5, Program-Status-Word Format.
↑ S390-ESA, p. 4-5, Program-Status-Word Format.
↑ z, pp. 4-5 –&#32, 4–8, Program-Status-Word Format.
↑ z, p. 4-8, Short PSW Format.

S360: IBM System/360 Principles of Operation (PDF) (Eighth ed.). IBM. September 1968. A22-6821-7.
func67: IBM System/360 Model 67 Functional Characteristics (PDF) (Third ed.). IBM. February 1972. GA27-2719-2.
S370: IBM System/370 Principles of Operation (PDF) (Eleventh ed.). IBM. September 1987. A22-7000-10.
S370-XA: IBM System/370 Extended Architecture Principles of Operation (PDF) (Second ed.). IBM. January 1987. SA22-7085-1.
S370-ESA: IBM Enterprise Systems Architecture/370 Principles of Operation (PDF) (First ed.). IBM. August 1988. SA22-7200-0.
z: z/Architecture Principles of Operation (PDF) (Thirteenth ed.). IBM. September 2019. SA22-7832-12.

This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.

[1] The nomenclature varies among architectures.

[12] However, a 360/67^[7] equipped with the Extended Dynamic Address Translation^[8] feature has a 32-bit mode selected by bit 4 of the PSW^[9] in Extended PSW mode^[8] (Control Register 6, bit 8^[10]).

[13] Despite the name, the 350/20 does not adhere to the S/360 architecture.

[27] Bit 22 is renamed as HFP exponent underflow in ESA/390

[28] Bit 23 is renamed as HFP significance in ESA/390

[FOOTNOTES360-2] S360.

[FOOTNOTES370-3] S370.

[FOOTNOTES370-XA-4] S370-XA.

[FOOTNOTES370-ESA-5] S370-ESA.

[FOOTNOTES390-ESA-6] S390-ESA.

[FOOTNOTEz-7] z.

[FOOTNOTEfunc67-8] unc67.

[FOOTNOTEfunc6757[httpbitsaversorgpdfibm360funcCharGA27-2719-2_360-67_funcCharpdfpage57_Glossary]-9] 1 2 func67, p. 57, Glossary.

[FOOTNOTEfunc6715[httpbitsaversorgpdfibm360funcCharGA27-2719-2_360-67_funcCharpdfpage15_Instruction_Fetching_and_Execution]-10] unc67, p. 15, Instruction Fetching and Execution.

[FOOTNOTEfunc6716[httpbitsaversorgpdfibm360funcCharGA27-2719-2_360-67_funcCharpdfpage16_Table_4._Control_Registers]-11] unc67, p. 16, Table 4. Control Registers.

[FOOTNOTES36015[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage16_Program_Status_Word]-14] S360, p. 15, Program Status Word.

[FOOTNOTES36015–16[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage15_Interruption]-15] S360, pp. 15–16, Interruption.

[FOOTNOTES37015–16[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage16_Interruption]-16] S370, pp. 15–16, Interruption.

[FOOTNOTES370156[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage177_Instruction-Length_Code]-17] S370, p. 156, Instruction-Length Code.

[FOOTNOTEfunc6715–16[httpbitsaversorgpdfibm360funcCharGA27-2719-2_360-67_funcCharpdfpage15_Instruction_Fetching_and_Execution]-18] unc67, pp. 15–16, Instruction Fetching and Execution.

[FOOTNOTES360156[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage177_Instruction-Length_Code]-19] S360, p. 156, Instruction-Length Code.

[FOOTNOTES3704-8_–&#32,_4–9[httpbitsaversorgpdfibm370princOpsGA22-7000-10_370_Principles_of_Operation_Sep87pdfpage81_Program-Status_Word_Format_in_BC_Mode]-20] S370, pp. 4-8 –&#32, 4–9, Program-Status Word Format in BC Mode.

[FOOTNOTES3706-3_–&#32,_6–5[httpbitsaversorgpdfibm370princOpsGA22-7000-10_370_Principles_of_Operation_Sep87pdfpage154_Interruption_Action]-21] S370, pp. 6-3 –&#32, 6–5, Interruption Action.

[FOOTNOTES3706-7_–&#32,_6–9[httpbitsaversorgpdfibm370princOpsGA22-7000-10_370_Principles_of_Operation_Sep87pdfpage158_Instruction-Length_Code]-22] S370, pp. 6-7 –&#32, 6–9, Instruction-Length Code.

[FOOTNOTES3704-6_–&#32,_4–7[httpbitsaversorgpdfibm370princOpsGA22-7000-10_370_Principles_of_Operation_Sep87pdfpage79_Program-Status_Word_Format_in_EC_Mode]-23] S370, pp. 4-6 –&#32, 4–7, Program-Status Word Format in EC Mode.

[FOOTNOTES370-XA4-5[httpbitsaversorgpdfibm370princOpsSA22-7085-1_370-XA_Principles_of_Operation_Jan87pdfpage76_Program-Status-Word_Format]-24] S370-XA, p. 4-5, Program-Status-Word Format.

[FOOTNOTES370-ESA4-5[httpbitsaversorgpdfibm370princOpsSA22-7200-0_370-ESA_Principles_of_Operation_Aug88pdfpage82_Program-Status-Word_Format]-25] S370-ESA, p. 4-5, Program-Status-Word Format.

[FOOTNOTES390-ESA4-5[httppublibzboulderibmcomepubspdfdz9ar008pdfpage115_Program-Status-Word_Format]-26] S390-ESA, p. 4-5, Program-Status-Word Format.

[FOOTNOTEz4-5_–&#32,_4–8[httppublibfpboulderibmcomepubspdfa227832cpdfpage199_Program-Status-Word_Format]-29] z, pp. 4-5 –&#32, 4–8, Program-Status-Word Format.

[FOOTNOTEz4-8[httppublibfpboulderibmcomepubspdfa227832cpdfp202_Short_PSW_Format]-30] z, p. 4-8, Short PSW Format.

[lower-alpha 1]

[1]

[2]

[3]

[4]

[5]

[6]

[lower-alpha 2]

[lower-alpha 3]

[11]

[12]

[13]

[14]

[15]

[16]

[17]

[18]

[19]

[20]

[21]

[22]

[23]

[lower-alpha 4]

[lower-alpha 5]

[24]

[25]

[7]

[8]

[9]

[10]