Verilog-AMS

Verilog-AMS是Verilog 硬件描述语言的一个衍生。它包含了模拟和混合信号扩展模块，以实现对于模拟电路和混合信号系统行为的描述。它扩展了Verilog、SystemVerilog等的事件驱动仿真器的回路，通过使用一个连续时间仿真器，可以在模拟域（）上求解微分方程。模拟事件可以触发数字行为，反之亦可。[1]

参考文献

Scheduling semantics are specified in the Verilog/AMS Language Reference Manual, section 8.

外部链接

I. Miller and T. Cassagnes, "Verilog-AMS Eases Mixed Mode Signal Simulation," Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems, pp. 305-308, Available: https://web.archive.org/web/20070927051749/http://www.nsti.org/publ/MSM2000/T31.01.pdf

一般的资料

Accellera Verilog Analog Mixed-Signal Group
verilog-ams.com
The Designer's Guide Community, Verilog-A/MS （页面存档备份，存于） — Examples of models written in Verilog-AMS]
EDA.ORG AMS Wiki（页面存档备份，存于） - Issues, future development, SystemVerilog integration

开源资料

OpenVAMS, a Open-Source VerilogAMS-1.3 Parser with internal VPI-like representation （页面存档备份，存于）
V2000 project - Verilog-AMS parser & elaborator （页面存档备份，存于）

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