AND-OR-invert (AOI) logic and AOI gates are two-level compound (or complex) logic functions constructed from the combination of one or more AND gates followed by a NOR gate. Construction of AOI cells is particularly efficient using CMOS technology, where the total number of transistor gates can be compared to the same construction using NAND logic or NOR logic. The complement of AOI logic is OR-AND-invert (OAI) logic, where the OR gates precede a NAND gate.^[1]

Overview

Most logic optimization result in a sum-of-products or product-of-sums logic expression.^[2]

AOI is used for sum-of-products, the variables are ANDed to form minterms which are ORed together then inverted, such as:

• AB + CD
• ABC + DEF
• ABCD + EFGH
• ABCDE + FGH + JK
• and other variations

Logic operations

AOI gates perform one or more AND operations followed by an OR operation then an inversion.

2-2 AOI gate

2-2 AOI symbol

Schematic of 74LS51 IC consists of a 3-3 AOI gate and 2-2 AOI gate^[3]

The 2-2 AOI gate can be represented by the following boolean equation and truth table:

${\displaystyle Q={\overline {(A\wedge B)\vee (C\wedge D)}}.}$

2-2 AOI
INPUT A   B   C   D				OUTPUT Q
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	0
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	0
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	0
1	1	0	0	0
1	1	0	1	0
1	1	1	0	0
1	1	1	1	0

2-1 AOI gate

2-1 AOI symbol

The 2-1 AOI gate can be represented by the following boolean equation and truth table:

${\displaystyle Q={\overline {A\vee (B\wedge C)}}.}$

2-1 AOI
INPUT A   B   C			OUTPUT Q
0	0	0	1
0	0	1	1
0	1	0	1
0	1	1	0
1	0	0	0
1	0	1	0
1	1	0	0
1	1	1	0

Electronic implementation

An AOI21 logic gate in CMOS using a complex gate (left) and standard gates (right)

Pinout of 74LS51 IC

AND-OR-invert (AOI) and OAI gates can be readily implemented in CMOS circuitry. AOI gates are particularly advantaged in that the total number of transistors (or gates) is less than if the AND, NOT, and OR functions were implemented separately. This results in increased speed, reduced power, smaller area, and potentially lower fabrication cost. For example, a 2-1 AOI gate can be constructed with 6 transistors in CMOS, compared to 10 transistors using a 2-input NAND gate (4 transistors), an inverter (2 transistors), and a 2-input NOR gate (4 transistors).

In NMOS logic, the lower half of the CMOS circuit is used in combination with a load device or pull-up transistor (typically a depletion load or a dynamic load).

AOI gates are similarly efficient in transistor–transistor logic (TTL).

Examples

TTL 7400-series logic family: (in past decades, a number of AOI parts were available in the 7400 family, but currently most are obsolete)

• SN5450 = dual 2-2 AOI gate, one is expandable^[4] (SN54 is military version of SN74)
• SN74LS51 = 2-2 AOI gate and 3-3 AOI gate^[3]
• SN54LS54 = single 2-3-3-2 AOI gate^[5]

CMOS 4000-series logic family:

• CD4085B = dual 2-2 AOI gate^[6]
• CD4086B = single expandable 2-2-2-2 AOI gate"^[7]
• CD4048B = single expandable 8-input 8-function with three-state output, 8 choices for gate type: 8 NOR / 8 OR / 8 NAND / 8 AND / 4-4 AND-OR-Invert / 4-4 AND-OR / 4-4 OR-AND-Invert / 4-4 OR-AND^[8]

See also

Wikimedia Commons has media related to AND-OR-NOT gates.

• List of 7400-series integrated circuits
• List of 4000-series integrated circuits

References

• Tinder, Richard F. (2000). Engineering digital design: Revised Second Edition. pp. 317–319. ISBN 0-12-691295-5. Retrieved 2008-07-04.
• John, Michael (1997). Application-Specific Integrated Circuits. Retrieved 2008-07-04.