The F-14's Central Air Data Computer, also abbreviated as CADC, computes altitude, vertical speed, air speed, and mach number from sensor inputs such as pitot and static pressure and temperature.[1] Earlier air data computer systems were electromechanical computers, such as in the F-111.[2] From 1968 to 1970, the first CADC to use custom digital integrated circuits was developed for the F-14.[3]
History
The CADC was a multi-chip integrated flight control system developed by Garrett AiResearch and used in early versions of the US Navy's F-14 Tomcat fighter. It is notable for early use of MOS custom integrated circuits and has been claimed as the first microprocessor.[3] The first microprocessor existing on a single chip was the contemporary Intel 4004. However, the 4004 did not have nearly the computing power or interfacing capability required to perform the functions of the CADC; at the time, the best integrated circuit (chip) technology available lacked the scale (number of transistors per chip) necessary to build a single-chip microprocessor for a flight control system.
The CADC was designed and built by a team led by Steve Geller and Ray Holt, and supported by the startup American Microsystems. Design work started in 1968 and was completed in June 1970, beating out a number of electromechanical systems that had also been designed for the F-14. It was classified by the Navy[4] until 1998. Ray Holt's story of this design and development is presented in his autobiography The Accidental Engineer.[3]
The CADC consisted of an A-to-D converter, several quartz pressure sensors, and a number of MOS-based microchips. Inputs to the system included the primary flight controls, a number of switches, static and dynamic air pressure (for calculating stall points and aircraft speed) and a temperature gauge. The outputs controlled the primary flight controls, wing sweep, the F-14's leading edge "glove vane", and the flaps.
The MP944 ran at 375 kHz. It contained six chips used to build the CADC, all based on a 20-bit fixed-point-fraction two's complement number system. They were the parallel multiplier unit (PMU) in a 28-pin DIP, the parallel divider unit (PDU) (28-pin DIP), the random-access storage (RAS) (14-pin DIP), the read-only memory (ROM) (14-pin DIP), the special logic function (SLF) (28-pin DIP), and the steering logic unit (SLU) (28-pin DIP). The complete system of 28 circuits consists of 1 PMU, 1 PDU, 1 SLF, 3 RASs, 3 SLUs, and 19 ROMs, enabled by 74,442 transistors.[5]
In 1971, Holt wrote an article about the system for Computer Design magazine,[6] but the Navy classified it, and finally released it in 1998.
References
- ↑ Dictionary of Military and Associated Terms. DIANE Publishing. Oct 1, 1987. p. 63. ISBN 9780941375108.
- ↑ F-111 Aardvark Pilot's Flight Operating Manual. United States Air Force. August 2007. p. 1–57. ISBN 9781430312123.
- 1 2 3 Holt, Raymond; Sorge, Leo (2017). The Accidental Engineer. Lulu.com. p. 36. ISBN 9781387313488. Archived from the original on 26 December 2020. Retrieved 2 June 2020.
- ↑ Dixit, Sudhir; Prasad, Ramjee (2017). Human Bond Communication: The Holy Grail of Holistic Communication and Immersive Experience. 9781119341338. p. 211. ISBN 9781119341338. Archived from the original on 26 December 2020. Retrieved 2 June 2020.
- ↑ "Ray Holt and the history of MP944/Cadc @ Rome Technopole, 2017 - YouTube". www.youtube.com. Archived from the original on 2020-12-26. Retrieved 2020-11-06.
- ↑ 1971 paper on the CADC (which was classified and never published)