Joel Emer
Born
Chicago, United States
NationalityAmerican
Alma materPurdue University
University of Illinois, Urbana-Champaign
Known forquantitative approach to processor evaluation, contributions to micro-architecture, Asim simulator
AwardsEckert–Mauchly Award, IEEE Fellow, ACM Fellow
Scientific career
Institutionscurrently Nvidia and MIT CSAIL; formerly Intel, Compaq and Digital Equipment Corporation
Doctoral advisorEdward S. Davidson

Joel S. Emer (born March 2, 1954)[1] is a pioneer in computer performance analysis techniques and a microprocessor architect. He is currently a researcher at Nvidia,[2] and a Professor of the Practice at MIT,[3] and was formerly an Intel Fellow. He was the 2009 recipient of the Eckert–Mauchly Award,[4] an ACM/IEEE joint award for contributions to computer and digital systems architecture.

Emer received his Ph.D. degree from the University of Illinois, Urbana-Champaign under the supervision of Prof. Edward S. Davidson. His first job immediately after graduation was at Digital Equipment Corporation where he initially worked on VAX performance evaluation and then on Alpha performance evaluation. As a consequence of his performance evaluation work, he became a pioneer in the quantitative approach to computer architecture. In conjunction with the development and application of various performance analysis techniques, he contributed a variety of research and advanced development ideas that were incorporated into various VAX and Alpha designs.

He is well known, along with his co-author Douglas W. Clark, for a seminal paper on the quantitative analysis of processor architectures,[5] which was published in the 11th International Symposium on Computer Architecture. That paper also contained the result that the VAX-11/780's performance was actually 0.5 MIPS instead of 1 MIPS as was previously claimed by DEC. That result helped popularize what Clark called the iron law of processor performance that related cycles per instruction (CPI), frequency and number of instructions to computer performance.

Emer has also contributed to simultaneous multithreading (SMT),[6] memory dependence prediction via store sets, and soft error analysis, and led the development of the Asim simulator.

In 2020, Emer was elected as a member into the National Academy of Engineering for quantitative analysis of computer architecture and its application to architectural innovation in commercial microprocessors.

References

  1. ↑ "Intel Fellow - Joel S. Emer". Retrieved 20 March 2016.
  2. ↑ "Joel Emer". nvidia.
  3. ↑ "Joel Emer". MIT.
  4. ↑ "ACM, IEEE-CS Honor Processor Architect Who Bridged Industry-Academic Divide". 14 April 2009. Archived from the original on 30 December 2010.
  5. ↑ A Characterization of Processor Performance in the VAX-11/780, Joel S. Emer, Douglas W. Clark, 1984, lEEE
  6. ↑ "Multithreading -- Mark Smotherman". Retrieved 20 March 2016.
Notes
  • Emer, Joel S.; Clark, Douglas W. (1984). "A characterization of processor performance in the VAX-11/780". Proceedings of the 11th Annual International Symposium on Computer Architecture. pp. 301–310.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.