ST62E40 microcontroller, based on the ST6 architecture

The ST6 and ST7 are 8-bit microcontroller product lines from STMicroelectronics. They are commonly used in small embedded applications like washing machines.

Although they use similar peripherals and are marketed as part of the same product line,[1][2] the two architectures are actually quite different.

Both have an 8-bit accumulator used for most operations, plus two 8-bit index registers (X and Y) used for memory addressing. Also both have 8-bit instructions followed by up to 2 bytes of operands, and both have support for manipulating and branching on individual bits of memory.

There, the similarities end.

The ST6 is a Harvard architecture with an 8-bit (256 byte) data address space and a separate 12-bit (4096 byte) program space. Operands are always 1 byte long, and some instructions support two operands, such as "move 8-bit immediate to 8-bit memory address". Subroutine calls are done using a separate hardware stack. Data registers (but not the program counter or flags) are memory-mapped.

The ST6's addressing modes are limited to immediate, 8-bit absolute memory address, and register indirect modes (X) and (Y).

The ST7 is a von Neumann architecture with a single 16-bit (64 kiB) address space. The first 256 bytes of RAM (the zero page) have extra flexibility. There are no two-operand instructions except for "test bit and branch". Its registers are not memory-mapped, and it uses general-purpose RAM (plus a stack pointer register) for subroutine calls.

The ST7 supports a wide variety of addressing modes, including base+index and double-indirect.

Three members of the ST6 microcontroller family: ST62E01, ST62E20, ST62E25

ST6 architecture

The ST6 has 64 bytes of RAM and 4096 bytes of program ROM. Larger amounts are accessed by bank-switching the low 2K section of the ROM.

The RAM address space is actually 256 bytes, divided as follows:

  • 063: Not implemented
  • 64127: Bank-switchable window into program ROM and data EPROM.
  • 128191: General-purpose RAM
  • 192255: Peripheral control registers (GPIO ports, timers, etc.) The accumulator is mapped at address 255, but is more commonly addressed implicitly.

Not mapped into the address space is a 12-bit program counter and an associated hardware stack (four or six levels deep, depending on model). There are only two status bits (carry and zero), and they are banked based on processor mode, with separate status bits for normal, interrupt and non-maskable interrupt operation.

The first four general-purpose RAM locations are also known as the X, Y, V and W registers, and some instructions can access them using special short addressing modes. The X and Y registers serve as index registers, and can use indirect addressing modes (X) and (Y).

The instruction set consists of one byte of opcode, followed by up to two one-byte operands. The instruction set can be summarized as follows:

ST6 family instruction set[3]
76543210b2b3MnemonicCZDescription
offsetopc0Conditional branches (5-bit PC-relative)
offset000JRNZ addressJump to PC + simm5 if Z == 0
offset100JRZ addressJump to PC + simm5 if Z == 1
offset010JRNC addressJump to PC + simm5 if C == 0
offset110JRC addressJump to PC + simm5 if C == 1
imm4c001imm8Unconditional branches (12-bit absolute)
imm40001imm8CALL imm12Push PC, jump to 12-bit address
imm41001imm8JP imm12Jump to 12-bit address
00101(reserved)
regc1c101Register operations (on X, Y, V or W)
reg010101INC regZIncrement register. Z is set, C is not.
reg110101LD A,regZA := {X, Y, V or W}
reg011101DEC regZDecrement register. Z is set, C is not.
reg111101LD reg,AZ{X, Y, V or W} := A
opcode01101Miscellaneous operations
00001101addrimm8LDI addr,imm8Set RAM to 8-bit immediate value
10001101(reserved)
01001101RETIReturn from interrupt. Pop PC, restore flags.
11001101RETReturn from subroutine. Pop PC from hardware stack.
00101101COM AZCComplement: C := msbit(A); A := ~A
10101101RLC ACA := A + A + C
01101101STOPHalt processor, clock, most peripherals until next interrupt
11101101WAITHalt processor until next interrupt; clock continues
bitopc011address ?Bit operations (absolute address only)
bit00011srcsimm8JRR bit,src,addressCC := src.bit; jump to PC+simm8 if reset (clear)
bit10011srcsimm8JRS bit,src,addressCC := src.bit; jump to PC+simm8 if set
bit01011dstRES bit,dstReset (set to 0) dst.bit
bit11011dstSET bit,dstSet (to 1) dst.bit
opcodedata111 ?ALU operations with RAM or immediate
opcode00111(X)Operand is (X)
opcode01111(Y)Operand is (Y)
opcode10111imm8imm8Operand is 8-bit immediate (source only)
opcode11111addraddrOperand is 8-bit RAM address
000src111 ?LD A,srcZA := src
100dst111 ?LD dst,AZdst := A (immediate forbidden)
010src111 ?ADD A,srcZCA := A + src
110src111 ?SUB A,srcZCA := A − src
001src111 ?CP A,srcZCA − src
101src111 ?AND A,srcZA := A & src
011dst111 ?INC dstZdst := dst + 1 (immediate forbidden)
111dst111 ?DEC dstZdst := dst − 1 (immediate forbidden)

†: ^ a b Confusingly, different models of the ST6 family use different conventions for the value of the carry bit after a subtraction. ST60 processors use the "carry" convention, which clears the bit if the subtract underflows, while the ST62 and ST63 processors use the "borrow" convention, which sets the bit in that case.[3]:21–22,42

ST7 architecture

The ST7 has six registers: the accumulator, X and Y index registers, stack pointer, program counter, and condition code register. Also, double-indirect addressing allows the zero page of RAM to serve as additional registers. An unusual but useful feature is that an interrupt pushes four of these registers on the stack (A and X as well as the usual PC and CC), and interrupt return restores them.

ALU instructions fall into two categories, two-operand and one-operand.

Two-operand instructions use the accumulator as the first source. The addressing mode specifies the second source, which may be:

  • 8-bit immediate
  • 8-bit absolute address
  • 16-bit absolute address
  • Indexed (X)
  • Indexed plus 8-bit offset (address8,X)
  • Indexed plus 16-bit offset (address16,X)

The destination is usually the accumulator, but a few instructions modify the second source. (Immediate operands are forbidden in such cases.)

One-operand instructions use the specified operand for both source and destination. The operand may be:

  • The accumulator A
  • The X register
  • 8-bit absolute address
  • Indexed (X)
  • Indexed plus 8-bit offset (address8,X)

Register plus offset computes a full-width sum, so the 8-bit form may address memory up to 255+255 = 510.

In addition to the above, there are three prefix bytes which may be prepended to any instruction for which they make sense:

  • PDY (0x90) changes all references to the X register to Y. This allows (Y), (address8,Y) and (address16,Y) addressing modes. This affects implicit operands as well, so the "load X" instruction becomes "load Y". A consequence of this is that load X can only use the X-relative addressing modes, and load Y can only use the Y-relative ones.
  • PIX (0x92) adds an indirection step to the instruction. The 8- or 16-bit address following the opcode byte is replaced by an 8-bit address of a memory location which holds an 8- or 16-bit address (the latter in big-endian order). This may then be indexed by the X register as usual. This allows (address8), (address16), ([address8],X) and ([address8.w],X) addressing modes.
  • PIY (0x91) combines the above effects. This allows the ([address8],Y) and ([address8.w],Y) addressing modes. (It may also be used with other modes as part of the "load Y" and "store Y" instructions.)
ST7 family instruction set[4]
76543210b2b3MnemonicDescription
000cbitvaddress ?Bit operations
0000bit0addr8soff8BTJT addr8,#bit,labelJump to PC + soff8 if source bit is true (set)
0000bit1addr8soff8BTJF addr8,#bit,labelJump to PC + soff8 if source bit is false (clear)
0001bit0addr8BSET addr8,#bitSet specified bit to 1
0001bit1addr8BRES addr8,#bitReset (clear) specified bit to 0
0010conditionsoff8Conditional branches (8-bit relative offset)
00100000soff8JRA labelBranch always (true)
00100001soff8JRF labelBranch never (false)
00100010soff8JRUGT labelBranch if unsigned greater than (C=0 and Z=0)
00100011soff8JRULE labelBranch if unsigned less than or equal (C=1 or Z=1)
00100100soff8JRNC labelBranch if no carry (C=0)
00100101soff8JRC labelBranch if carry (C=1)
00100110soff8JRNE labelBranch if not equal (Z=0)
00100111soff8JREQ labelBranch if equal (Z=1)
00101000soff8JRNH labelBranch if not half-carry (H=0)
00101001soff8JRH labelBranch if half-carry (H=1)
00101010soff8JRPL labelBranch if plus (N=0)
00101011soff8JRMI labelBranch if minus (N=1)
00101100soff8JRNM labelBranch if not interrupt mask (M=0)
00101101soff8JRM labelBranch if interrupts masked (M=1)
00101110soff8JRIL labelBranch if interrupt line is low
00101111soff8JRIH labelBranch if interrupt line is high
0modeopcode ?One-operand instructions
0011opcodeaddr8OP addr88-bit absolute address
0100opcodeOP AAccumulator
0101opcodeOP XX register (Y register with prefix)
0110opcodeaddr8OP (addr8,X)8-bit address plus X
0111opcodeOP (X)Indexed with no offset
0mode0000 ?NEG operandTwo's-complement negate
0mode0001 ?(reserved)
0mode0010 ?(reserved)
01000010MUL X,AX:A := X × A. (MUL Y,A with prefix)
0mode0011 ?CPL operandOnes' complement, logical not
0mode0100 ?SRL operandShift right logical. Msbit cleared, lsbit to carry.
0mode0101 ?(reserved)
0mode0110 ?RRC operandRotate right through carry, (operand:C) := (C:operand)
0mode0111 ?SRA operandShift right arithmetic. Msbit preserved, lebit to carry.
0mode1000 ?SLL operandShift left. Msbit to carry.
0mode1001 ?RLC operandRotate left through carry.
0mode1010 ?DEC operandDecrement. (N and Z set, carry unaffected)
0mode1011 ?(reserved)
0mode1100 ?INC operandIncrement. (N and Z set, carry unaffected)
0mode1101 ?TNZ operandTest non-zero. Set N and Z based on operand.
0mode1110 ?SWAP operandSwap halves of operand (4-bit rotate).
0mode1111 ?CLR operandSet operand to 0. N and Z set to fixed values.operand.
100opcodeMiscellaneous instructions. None implicitly set the condition codes.
10000000IRETReturn from interrupt (pop CC, A, X, PC)
10000001RETReturn from subroutine (pop PC)
10000010TRAPForce trap interrupt
10000011(reserved)
10000100POP APop A from stack
10000101POP XPop X from stack
10000110POP CCPop condition codes from stack
10000111(reserved)
10001000PUSH APush A onto stack
10001001PUSH XPush X onto stack
10001010PUSH CCPush condition codes onto stack
10001011(reserved)
1000110(reserved)
10001110HALTHalt processor and clocks
10001111WFIWait for interrupt, halting processor but not clocks
10010000PDYInstruction prefix; swap X and Y in next instruction
10010001PIYInstruction prefix; PDY plus PIX
10010010PIXInstruction prefix; use 8-bit memory indirect for operand
10010011LD X,YX := Y. With PDY, does "LD Y,X".
10010100LD S,XS := X. Load stack pointer.
10010101LD S,AS := A. Load stack pointer.
10010110LD X,SX := S.
10010111LD X,AX := A.
10011000RCFReset (clear) carry flag
10011001SCFSet carry flag
10011010RIMReset interrupt mask (enable interrupts)
10011011SIMSet interrupt mask (disable interrupts)
10011100RSPReset stack pointer (to top of RAM)
10011101NOPNo operation. (=LD A,A)
10011110LD A,SA := S
10011111LD A,XA := X.
1modeopcodevalue ?Two-operand instructions A := A op operand
1010opcodeimm8OP #imm88-bit immediate operand (forbidden as destination)
1011opcodeaddr8OP addr88-bit absolute address
1100opcodeaddrhiaddrloOP addr1616-bit absolute address
1101opcodeaddrhiaddrloOP (addr16,X)Indexed with 16-bit offset
1110opcodeaddr8OP (addr8,X)Indexed with 8-bit offset
1111opcodeOP (X)Indexed with no offset
1mode0000value ?SUB A,operandA := A operand
1mode0001value ?CP A,operandCompare A operand
1mode0010value ?SBC A,operandSubtract with borrow A := A operand C
1mode0011value ?CP X,operandCompare X operand
1mode0100value ?AND A,operandA := A & operand, bitwise and
1mode0101value ?BCP A,operandBitwise test A & operand
1mode0110value ?LD A,operandLoad A := operand
10100111imm8(reserved, =LD #imm8,A)
1mode0111value ?LD operand,AStore operand := A
1mode1000value ?XOR A,operandA := A ^ operand, exclusive-or
1mode1001value ?ADC A,operandA := A + operand + C, add with carry
1mode1010value ?OR A,operandA := A | operand, inclusive or
1mode1011value ?ADD X,operandA := A + operand
10101100imm8x(reserved, =JP #imm8)
1mode1100value ?JP operandPC := operand, unconditional jump
10101101soff8CALLR labelPUSH PC, PC := PC + operand
1mode1101value ?CALL operandPush PC, PC := operand
1mode1110value ?LD X,operandLoad X := operand
10101111imm8(reserved, =LD #imm8,X)
1mode1111value ?LD operand,XStore operand := X

References

  1. Datasheet: ST62T00C/T01C from 1998
  2. "2006 EDN Microcontroller/Microprocessor directory, 8-bit microprocessors sorted by Instruction Set Architecture" (PDF). p. 26. 100616 edn.com
  3. 1 2 "ST6 Family Programming Manual" (PDF). Revision 2.0. STMicroelectronics. October 2004. Retrieved 2017-02-28.
  4. "ST7 Family Programming Manual" (PDF). Revision 2. STMicroelectronics. November 2005. Retrieved 2017-02-28.
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