The New York University's Ultracomputer is a significant processor design in the history of parallel computing. The system has N processors, N memories, and an N log N message-passing switch connecting them. The system supported an innovative fetch-and-add process coordination instruction, and the custom VLSI network switches could combine references (including fetch-and-adds) from several processors into a single reference, to reduce memory contention.

The machine was developed in the 1980s at the Courant Institute of Mathematical Sciences Computer Science Department, based on a concept developed by Jacob T. Schwartz.[1] Most of the work done was theoretical, but two prototypes were built:[2][3]

  • An 8-processor bus-based machine
  • A 16-processor, 16 memory-module machine with custom VLSI switches supporting the fetch-and-add instruction.

Ultracomputer technology was the basis for the IBM Research Research Parallel Processor Prototype (RP3), an experimental parallel computer that supported 512 processing nodes. A 64-node system was built at the Thomas J. Watson Research Center in the late 1980s.[4]

References

  1. ↑ Jacob T. Schwartz (October 1980). "Ultracomputers". ACM Transactions on Programming Languages and Systems. 2 (4): 484–521. doi:10.1145/357114.357116.
  2. ↑ The NYU Ultracomputer Project
  3. ↑ Allan Gottlieb (October 1987). An Overview of the NYU Ultracomputer Project (PDF) (Report). Ultracomputer Note #100, New York University. Retrieved October 30, 2016.
  4. ↑ W. David Gardner (May 4, 1987). "IBM Puts Together RP3 and GF11". InformationWeek. p. 50.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.